Single poly non-volatile memory structure and its fabricating method

ABSTRACT

The present invention discloses a single poly non-volatile memory structure includeing a semiconductor substrate with two active areas divided by isolation regions. A control gate doped with N-type impurities is embedded in the first active area, and a first floating gate is formed thereon. A second floating gate is formed on the substrate of the second active area, and two doped regions are implanted at opposite sides of the second active areas in the substrate. A floating gate line is employed to connect the first and second floating gate for making sure that the two floating gates are in the same potential. When the control gate is biased to a voltage level, the voltage level would be coupled to the first floating gate so as to keep the second floating gate in the same potential with the first floating gate. While one of the doped regions is biased to a voltage level, electrons would eject from the other doped region and trapped in the floating gates, thereby preserving information in this memory structure.

FIELD OF THE INVENTION

[0001] The present invention relates to a non-volatile memory structureformed in and on a semiconductor substrate. More particularly, theinvention relates to a non-volatile memory structure with a single layerof ploy gate and a method for fabricating the structure.

BACKGROUND OF THE INVENTION

[0002] A non-volatile memory cell, a widely used semiconductor device,is capable to preserve digital information without supply of electricpower. An erasable programmable ROM (EPROM), one of the non-volatilememory cells fabricated based on a semiconductor substrate, preservesdigital information by trapping electrons in its floating gate when someelectrodes of the EPROM are biased in desired levels. The electronstrapped in the floating gate of EPROM could be evacuated to erase thepreserved information by exposing the EPROM in an environment with ahigh dose of ultraviolet. Since the EPROM has the feature of repeatedlyrecording information in a state out of supply of electric power, it isemployed in many electronic devices nowadays.

[0003] Referring to FIG. 1, an EPROM cell is fabricated on a siliconsubstrate 102 doped with P-type impurities, such as B, BF₂ ⁺. A silicondioxide layer 108 formed on the surface of the P-substrate 102encompasses a floating gate 110 and control gate 112, in which the twogates are insulated by the silicon dioxide layer 108. A source region104 and drain region 106 doped with N-type impurities, such as P, As,are embedded at opposite two sides of the floating gate 110 in theP-type substrate 102. When recording information in the EPROM cell, thecontrol gate 112 and drain region 106 are biased in a high voltagelevel, meanwhile the source region 104 and substrate 102 beingelectrically connected to ground, to drive electrons ejecting from thesource region 104 through the silicon dioxide layer 108 into thefloating gate 110. The silicon dioxide layer 108 would construct apotential barrier so as to trap the electrons in the floating gate 110.Because of the electrons trapped in the floating gate, when the controlgate 112 is biased to its original threshold voltage level, the channelbetween the source region 104 and drain region 106 will not be normallyturned on, therefore regarding this state as “1”. Contrarily, if theEPROM cell doesn't be biased to eject electrons into the floating gate110, the channel between the source region 104 and drain region 106 willbe turned on, as long as the control gate 112 is biased to its thresholdvoltage level. Such a state would be regard as “0”.

[0004] To erase the preserved information, it needs to expose the EPROMin an ultraviolet environment for providing the trapped electrons enoughenergy to escape from the potential barrier of the silicon dioxide layer108. By applying the erasing and recording procedures, the EPROM cellcan be repeatedly performed to preserve digital information.

[0005] Commonly, the EPROM cell includes two stacked gates, the controlgate 112, and floating gate 110. To approach the two gates, it needsmore complicated fabricating processes to form the two-layer structure.For forming an EPROM chip, EPROM cells are always designed inassociation with logic devices, such as MOSFET, CMOSFET, and so on.However, the MOSFET and CMOSFET are both one-layer structures with fewerlithographic masks than those of the EPROM cells, so as to make thefabricating processes of the EPROM cell being somewhat incompatible fromthat of the MOSFET and CMOSFET. For fitting the fabricating processes ofthe EPROM cell, the processes of the EPROM chip would become costly andcomplicatedly.

[0006] The traditional EPROM cell could provide a high integration, butin some cases the EPROM chip doesn't need such a high integration butconcerns more about the cost and simplicity of fabricating processes.Under this concern, the present invention demonstrates a single polynon-volatile memory structure and its fabricating method for improvingthe disadvantages existed in the prior art.

SUMMARY OF THE INVENTION

[0007] A first object of the invention is to provide a non-volatilememory structure with a single-layer poly gate design for simplifyingthe fabricating processes of the structure so as to fit the processeswith those of logic devices, such as MOFET, COMFET.

[0008] A second object of the invention is to provide a method toapproach the single poly non-volatile memory structure.

[0009] The present invention provides a single poly non-volatile memorystructure including a P-type doped semiconductor substrate, in which anN-well is formed, divided into two active areas by isolation regions. Acontrol gate is embedded in the first active area by implanting N-typeimpurities into the N-well. A first floating gate as well as a secondfloating gate are formed on the control gate and the second active areathrough subsequently stacking an oxide, polysilicon, and silicide layerson the substrate, and then etching the oxide-polysilicon-silicidecomposite layer. Two doped regions are formed at opposite two sides ofthe second floating gate in the second active area by implanting N-typeimpurities. A floating gate line is formed to electrically connect thefirst floating gate and second floating gate for making sure that theywould keep in the same potential. When the control gate is biased to avoltage level, the voltage level would be coupled to the first floatinggate so as to keep the second floating gate in the same potential withthe first floating gate. While one of the doped regions is biased to avoltage level, electrons would eject from the other doped region andtrapped in the floating gates, thereby preserving information in thismemory structure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is a cross-sectional side view of a traditional EPROM cell;

[0011]FIG. 2 is a cross-sectional side view of a single polynon-volatile memory structure according to the invention;

[0012]FIG. 3 illustrates a cross-sectional side view of a semiconductorsubstrate with an N-well.

[0013]FIG. 4 illustrates a cross-sectional side view of thesemiconductor substrate with channel stop implantation;

[0014]FIG. 5 illustrates a cross-sectional side view of thesemiconductor substrate formed with isolation regions;

[0015]FIG. 6 illustrates a cross-sectional side view of thesemiconductor substrate embedded a doped buried layer and stacked anoxide layer and polysilicon layer;

[0016]FIG. 7 illustrates a cross-sectional side view of thesemiconductor substrate formed a tungsten silicide layer upon thepolysilicon layer;

[0017]FIG. 8 illustrates a cross-sectional side view of thesemiconductor substrate formed two floating gates and source/drainregions;

[0018]FIG. 9 illustrates a cross-sectional side view of thesemiconductor substrate fabricated with a single poly non-volatilememory structure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0019] The present invention provides a non-volatile memory structurewith a single poly-gate-layer design for improving the disadvantages ofrelatively high costs and complicated fabricating processes. Across-sectional side view of the non-volatile memory structure isdescribed fist for clarifying the mechanism of the structure. Afterward,an embodiment of fabricating processes would be illustrated to approachthe single poly non-volatile structure.

[0020] As shown in FIG. 2, a single poly non-volatile memory structureis established in and on a semiconductor substrate 202 doped with P-typeimpurities, in which an N-well 204 is formed. A doped buried layer 206is embedded in the N-well 204 for servicing as a control gate with ahigher dosage of N-type impurities than that of N-well 204. Thesemiconductor substrate 202 is divided into a first active area 201 andsecond active area 203 by isolation regions 208. A first oxide layer 210and first gate electrode 212 are subsequently formed upon the firstactive area 201 to construct a first floating gate 211. Similarly, asecond floating gate 215 is constructed by forming a second oxide layer214 and gate electrode 216. Beneath the opposite two sides of the secondfloating gate 215, a first doped region 218 a and second doped region218 b are formed in the second active area 203 to establish a channelbetween them by implanting N-type impurities. A floating gate line 220connects the first floating gate 211 with the second floating gate 215for balancing the two gates in a same potential while each of themvarying in voltage levels.

[0021] For recording information, the control gate 206 is biased througha word line 222 connected thereon. Since the first gate electrode 212,first oxide layer 210, and control gate 206 could be regarded as acapacitance, the potential of the control gate 206 biased through theword line 222 will be coupled to the first gate electrode 212 and holdthe second gate electrode 216 in the same potential of the firstfloating gate 211. In addition, the potential of the first floating gate211 could be achieved in different efficiencies by adjusting the ratiobetween the areas of the first floating gate 211 and the control gate206. If the voltage levels of the control gate 206 and second dopedregion 218 b, which is biased through a bit line 224, are high enough,electrons would easily ejects through the second oxide layer 214 intothe second gate electrode 216 and be trapped in the first and secondfloating gates, thereby achieving the function of preserving informationeven without supply of external electric power. Similar to the priorart, when the single poly non-volatile memory structure exposed in anenvironment with a high dose of ultraviolet, the electrons trapped inthe floating gates would escape from them and enable the memorystructure to record information again.

[0022]FIG. 3 shows initial steps of an embodiment to approach the singleploy non-volatile memory structure. A semiconductor substrate 302 dopedwith P-type impurities is provided, in which a N-well 304 is formed byimplanting N-type impurities, such as P, As. A pad oxide layer 306 isformed upon the surface of substrate 302 through a thermal oxidationtreatment. Thereafter, a nitride layer 308 is deposited on the pad oxidepreferably through a Low Pressure Chemical Vapor Deposition (LPCVD)method. For defining active areas, a photoresist layer 312 is patternedon the nitride layer 306 for serving as an etching mask through alithography process. The nitride layer 308 is then etched until the padoxide layer 306 is exposed.

[0023] Referring to FIG. 4, after the nitride layer 308 is etched, thephotoresist layer 312 (see FIG. 3) is stripped to remain parts of thenitride layer 308 for defining the active areas 401, 403. For completelyisolating the active area 403 form the active area 401, a channel stopimplantation is performed by patterning a photoresist layer 402 to maskthe first active area 401 and implanting P-type impurities to from afirst channel stop region 404 a and second channel stop region 404 b.After the implantation of the first and second channel stop regions 404a, 404 b, the photoresist layer 402 is stripped and the substrate 302 isthen thermally treated in an ambient with moisture and oxygen forgrowing thick field oxide layers (FOX) as isolation regions 502, asshown in FIG. 5. When the isolation regions, i.e. FOX, 502 are formed,the photoresist layer 402, nitride layer 308, and pad oxide layer 306are subsequently removed from the surface of substrate 302.

[0024]FIG. 5 shows a cross-sectional side view of the substrate 302 withisolation regions 502. It's noticed that the nitride layer 308 (see FIG.4) still exists on the surface of substrate 304, while performing theoxidation, for preventing moisture and oxygen penetrating into thesubstrate of active areas 401, 403. In this preferred embodiment, thecombinations of isolation regions 502 and channel stop regions 404 a,404 b are effective to suppress the interference between active areas401 and 403, however there are still other alternatives, such as trenchisolation is one of the widely used structures in this art.

[0025] Referring to FIG. 6, a gate oxide layer 602 is formed upon thesurface of substrate 302 preferably through a dry oxidation process. Apolysilicon layer 604 is formed upon the gate oxide layer 602 preferablythrough a Chemical Vapor Deposition (CVD) method. Thereafter, aphotoresist layer 606 is patterned on the surface of polysilicon layer604 to cover the second active area 403 for serving as a mask so as toprevent ions implanting into the second active area and allow to form adoped buried layer 608 in the first active area 401. In theimplantation, a higher dosage of N-type impurities than that of theN-well 302 is employed to form the doped buried layer 608 with a betterconductivity thereby serving as a control gate of the present singlepoly non-volatile memory structure. In this preferred embodiment, thedosage of N-type impurities of the doped buried layer is between about1×10¹⁵˜2×10¹⁵ cm⁻². It is noticed that, the buried layer could also beperformed prior the deposition of the polysilicon layer 604, but it maytrigger issues of degradation of conductivity of the buried layer 608due to the high temperature during the deposition.

[0026] Referring to FIG. 7, after the photoresist layer 606 is stripped(see FIG. 6), a tungsten silicide layer 702 is formed upon thepolysilicon layer 604 for improving the conductivity of the will-formedfloating gate electrodes. A photoresist layer 704 is formed on thesurface of tungsten silicide layer 702 to define floating gates of firstand second active areas. In this preferred embodiment, the tungstensilicide layer 702 is employed to deal the resistance issues of thewill-formed floating gate electrodes. However it's not the only option,a titanium suicide layer or cobalt suicide layer could also be one ofthe alternatives to substitute the tungsten silicide layer.

[0027] Referring to FIG. 8, a first floating gate 802 and secondfloating gate 804 are form by etching the oxide-poly-silicide compositelayer. Then, strip the photoresist layer 704 (see FIG. 7). Thereafter, aphotoresist layer 801 is patterned to cover the surface of first activearea 401 for serving as an implantation mask. For establishing a channelbeneath the second floating gate, N-type impurities are implanted atopposite two sides of second floating gate 804 in the substrate 302 toform a first doped region 806 a and second doped region 806 b. In thispreferred embodiment, the first and second doped regions 806 a, 806 bhave a dosage between about 3×10¹⁵˜4×10¹⁵ cm⁻². However, in generalcases the dosage could be tolerated in a region between about8×10¹²˜1.5×10¹³ cm⁻².

[0028]FIG. 9 shows an accomplished cross-sectional side view of thesingle poly non-volatile memory structure. After the formation of thefirst floating gate 802 and second floating gate 804, the photoresistlayer 801 is stripped. For achieving the present non-volatile memorystructure, a dielectric layer 902 is formed on the surface of substrate302. The dielectric layer 902 is preferred to be a material ofphosphosilicate glass (PSG), and the PSG layer is suggested to reflow tosmooth its surface. Through lithographic processes, several contactholes expose some areas of the control gate 608, first floating gate802, second floating gate, and second doped region. A conductive layeris then coated upon the dielectric layer and exposed areas, throughpatteming processes, thereby connecting the first floating gate with thesecond floating gate, and forming a plug contacting with the controlgate 608 for connecting a word line and the other plug contacting withthe second doped region 804 b for connecting a bit line.

[0029] Since the present memory structure has only one-layer design, itsfabricating processes would be easily fitted with those of logicdevices, such as MOSFET, COMSFET. Although this structure would decreasethe integration of a integrated circuit, in some cases of memory chipsin which the integration is not a crucial issue, this structure wouldeffectively simplifying fabricating processes and saving manufacturingcosts.

[0030] As is understood by a person skilled in the art, the foregoingpreferred embodiments of the present invention that are illustrated ofthe present invention rather than limiting of the present invention. Itis intended to cover various modifications and similar arrangementsincluded within the spirit and scope of the appended claims, the scopeof which should be accorded the broadest interpretation so as toencompass all such modifications and similar structure.

What is claimed is:
 1. A single poly non-volatile memory structure,which comprises: a semiconductor substrate having a first and secondactive areas divided by an isolation region; a control gate embedded inthe first active area and doped with impurities; a first floating gateformed upon the control gate; a second floating gate formed upon thesecond active area; a first doped region and second doped region formedat opposite two sides of the second floating gate in the second activearea to establish a channel between the first doped region and thesecond doped region; and a floating gate line connecting between thefirst floating gate and the second floating gate for allowing the firstfloating gate and the second floating gate in a same potential when thefirst floating gate generates the potential for responding to thevoltage level of the control gate, thereby driving electrons ejectingfrom the first doped region and trapped into the second floating gate.2. The memory structure of claim 1 further comprising a word linecontacting with the control gate and insulated from the floating gateline.
 3. The memory structure of claim 1 further comprising a bit linecontacting with the second doped region and insulated from the floatinggate line.
 4. The memory structure of claim 2 and claim 3 furthercomprising a dielectric layer formed on a surface of the semiconductorsubstrate for servicing as insulation among the first floating gate, thesecond floating gate, the floating gate line, the word line, and the bitline.
 5. The memory structure of claim 1 wherein the control gate isformed in an N-well of the semiconductor substrate and has a higherdosage of N-type impurity than the N-well does.
 6. The memory structureof claim 5 wherein the dosage of the control gate is between about1×10¹⁵˜2×10¹⁵ cm⁻².
 7. The memory structure of claim 1 wherein the firstfloating gate comprises an oxide layer formed on the first active areaand a polysilicon layer stacked on the oxide layer.
 8. The memorystructure of claim 7 further comprising a tungsten silicide layerstacked upon the polysilicon layer.
 9. The memory structure of claim 1wherein the second floating gate comprises an oxide layer formed on thefirst active area and a polysilicon layer stacked on the oxide layer.10. The memory structure of claim 9 further comprising a tungstensilicide layer stacked upon the polysilicon layer.
 11. A method forfabricating a single poly non-volatile memory structure comprisingfollowing steps: providing a semiconductor substrate with a first activearea and a second active area, the first active area being separatedfrom the second active area by an isolation region; forming a dopedburied layer in the first active area; forming a first floating gate onthe doped buried layer of the first active area and a second floatinggate on the second active area; forming a first and second doped regionsat opposite two sides of the second floating gate in the second activearea; and connecting the first floating gate and the second floatinggate with a floating gate line made of conductive material.
 12. Themethod of claim 11 further comprising following steps before forming thedoped buried layer: forming an oxide layer upon the first active areaand the second active area; and forming a polysilicon layer upon theoxide layer.
 13. The method of claim 12 further comprising followingsteps before forming the first floating gate and the second floatinggate: forming a tungsten silicide layer upon the polysilicon layer;lithographing a photoresist layer upon the tungsten silicide layer fordefining the first floating gate and the second floating gate; etchingthe tungsten silicide layer, polysilicon layer, and the oxide layer byemploying the photoresist layer as an etching mask; and stripping thephotoresist layer.
 14. The method of claim 11 further comprisingfollowing steps before connecting the first floating gate and the secondfloating gate: forming a dielectric layer covering the first floatinggate, the second floating, and a surface of the semiconductor substrate;patterning the dielectric layer for defining contact holes of the firstfloating gate, the second floating gate; forming a conductive layer uponthe dielectric layer and; patterning the conductive layer for shapingthe floating gate line.
 15. The method of claim 11 wherein the firstactive area is defined in an N-type doped region of the substrate. 16.The method of claim 1 1 wherein the second active area is defined in aP-type doped region of the substrate.
 17. The method of claim 11 whereinthe doped buried layer is formed by implanting N-type impurities intothe first active area.
 18. The method of claim 17 wherein the N-typeimpurities have a dosage between about 1×10¹⁵ ˜2×10¹⁵ cm⁻².
 19. Themethod of claim 11 wherein the first doped region and the second dopedregion are formed by implanting N-type impurities into the opposite twosides of the second floating gate in the second active area.
 20. Themethod of claim 19 wherein the first doped region and the second dopedregion have a dosage between about 8×10¹²˜1.5×10¹³ cm⁻².